This post provides supplementary information to the video that I have just posted on using GPIOs with the Beaglebone Black.
The Video
In this video I am going to continue my series on the Beaglebone by demonstrating how to use its GPIOs for both input and output applications. In this video I will wire simple input and output circuits that are attached to two GPIOs – one that lights an LED and the other that receives a button input. I covered this topic below before in a previous video. I am updating it here because there have been significant changes to the Linux kernel. This video will cover the Linux device tree for ARM embedded systems and explain how you can create custom device tree overlays to configure the GPIOs for your applications at run time from within the Linux userspace. I will explain the use of internal and external pullup and pulldown resistors and I will make available and describe a set of C++ code examples for reading and writing to the Beaglebone’s GPIOs. I have also built a set of PDF tables that aggregate the information that you need and make it easier to configure GPIOs on your Beaglebone’s P8 and P9 headers.
The code for this video is available by typing:
1 |
git clone git://github.com/derekmolloy/boneDeviceTree.git |
The information below is covered in the video, but here it is just in case you need to get a text view:
Getting started
We can get some information about the pins in use:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 |
root@beaglebone:/sys/kernel/debug/pinctrl/44e10800.pinmux# cat pingroups registered pin groups: group: pinmux_userled_pins pin 21 (44e10854) pin 22 (44e10858) pin 23 (44e1085c) pin 24 (44e10860) group: pinmux_rstctl_pins pin 20 (44e10850) group: pinmux_i2c0_pins pin 98 (44e10988) pin 99 (44e1098c) group: pinmux_i2c2_pins pin 94 (44e10978) pin 95 (44e1097c) group: pinmux_emmc2_pins pin 32 (44e10880) pin 33 (44e10884) pin 0 (44e10800) pin 1 (44e10804) pin 2 (44e10808) pin 3 (44e1080c) pin 4 (44e10810) pin 5 (44e10814) pin 6 (44e10818) pin 7 (44e1081c) group: pinmux_userled_pins pin 21 (44e10854) pin 22 (44e10858) pin 23 (44e1085c) pin 24 (44e10860) group: mcasp0_pins pin 107 (44e109ac) pin 103 (44e1099c) pin 101 (44e10994) pin 100 (44e10990) pin 106 (44e109a8) group: nxp_hdmi_bonelt_pins pin 108 (44e109b0) pin 40 (44e108a0) pin 41 (44e108a4) pin 42 (44e108a8) pin 43 (44e108ac) pin 44 (44e108b0) pin 45 (44e108b4) pin 46 (44e108b8) pin 47 (44e108bc) pin 48 (44e108c0) pin 49 (44e108c4) pin 50 (44e108c8) pin 51 (44e108cc) pin 52 (44e108d0) pin 53 (44e108d4) pin 54 (44e108d8) pin 55 (44e108dc) pin 56 (44e108e0) pin 57 (44e108e4) pin 58 (44e108e8) pin 59 (44e108ec) group: nxp_hdmi_bonelt_off_pins pin 108 (44e109b0) |
We can also get information about which pins are in use (allocated):
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 |
root@beaglebone:/sys/kernel/debug/pinctrl/44e10800.pinmux# cat pinmux-pins |more Pinmux settings per pin Format: pin (name): mux_owner gpio_owner hog? pin 0 (44e10800): mmc.5 (GPIO UNCLAIMED) function pinmux_emmc2_pins group pinmux_emmc2_pins pin 1 (44e10804): mmc.5 (GPIO UNCLAIMED) function pinmux_emmc2_pins group pinmux_emmc2_pins pin 2 (44e10808): mmc.5 (GPIO UNCLAIMED) function pinmux_emmc2_pins group pinmux_emmc2_pins pin 3 (44e1080c): mmc.5 (GPIO UNCLAIMED) function pinmux_emmc2_pins group pinmux_emmc2_pins pin 4 (44e10810): mmc.5 (GPIO UNCLAIMED) function pinmux_emmc2_pins group pinmux_emmc2_pins pin 5 (44e10814): mmc.5 (GPIO UNCLAIMED) function pinmux_emmc2_pins group pinmux_emmc2_pins pin 6 (44e10818): mmc.5 (GPIO UNCLAIMED) function pinmux_emmc2_pins group pinmux_emmc2_pins pin 7 (44e1081c): mmc.5 (GPIO UNCLAIMED) function pinmux_emmc2_pins group pinmux_emmc2_pins pin 8 (44e10820): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 9 (44e10824): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 10 (44e10828): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 11 (44e1082c): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 12 (44e10830): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 13 (44e10834): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 14 (44e10838): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 15 (44e1083c): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 16 (44e10840): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 17 (44e10844): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 18 (44e10848): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 19 (44e1084c): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 20 (44e10850): rstctl.3 (GPIO UNCLAIMED) function pinmux_rstctl_pins group pinmux_rstctl_pins pin 21 (44e10854): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 22 (44e10858): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 23 (44e1085c): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 24 (44e10860): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 25 (44e10864): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 26 (44e10868): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 27 (44e1086c): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 28 (44e10870): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 29 (44e10874): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 30 (44e10878): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 31 (44e1087c): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 32 (44e10880): mmc.5 (GPIO UNCLAIMED) function pinmux_emmc2_pins group pinmux_emmc2_pins pin 33 (44e10884): mmc.5 (GPIO UNCLAIMED) function pinmux_emmc2_pins group pinmux_emmc2_pins pin 34 (44e10888): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 35 (44e1088c): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 36 (44e10890): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 37 (44e10894): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 38 (44e10898): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 39 (44e1089c): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 40 (44e108a0): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 41 (44e108a4): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 42 (44e108a8): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 43 (44e108ac): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 44 (44e108b0): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 45 (44e108b4): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 46 (44e108b8): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 47 (44e108bc): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 48 (44e108c0): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 49 (44e108c4): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 50 (44e108c8): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 51 (44e108cc): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 52 (44e108d0): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 53 (44e108d4): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 54 (44e108d8): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 55 (44e108dc): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 56 (44e108e0): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 57 (44e108e4): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 58 (44e108e8): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 59 (44e108ec): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pins pin 60 (44e108f0): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 61 (44e108f4): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 62 (44e108f8): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 63 (44e108fc): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 64 (44e10900): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 65 (44e10904): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 66 (44e10908): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 67 (44e1090c): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 68 (44e10910): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 69 (44e10914): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 70 (44e10918): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 71 (44e1091c): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 72 (44e10920): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 73 (44e10924): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 74 (44e10928): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 75 (44e1092c): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 76 (44e10930): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 77 (44e10934): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 78 (44e10938): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 79 (44e1093c): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 80 (44e10940): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 81 (44e10944): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 82 (44e10948): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 83 (44e1094c): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 84 (44e10950): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 85 (44e10954): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 86 (44e10958): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 87 (44e1095c): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 88 (44e10960): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 89 (44e10964): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 90 (44e10968): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 91 (44e1096c): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 92 (44e10970): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 93 (44e10974): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 94 (44e10978): 4819c000.i2c (GPIO UNCLAIMED) function pinmux_i2c2_pins group pinmux_i2c2_pins pin 95 (44e1097c): 4819c000.i2c (GPIO UNCLAIMED) function pinmux_i2c2_pins group pinmux_i2c2_pins pin 96 (44e10980): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 97 (44e10984): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 98 (44e10988): 44e0b000.i2c (GPIO UNCLAIMED) function pinmux_i2c0_pins group pinmux_i2c0_pins pin 99 (44e1098c): 44e0b000.i2c (GPIO UNCLAIMED) function pinmux_i2c0_pins group pinmux_i2c0_pins pin 100 (44e10990): 48038000.mcasp (GPIO UNCLAIMED) function mcasp0_pins group mcasp0_pins pin 101 (44e10994): 48038000.mcasp (GPIO UNCLAIMED) function mcasp0_pins group mcasp0_pins pin 102 (44e10998): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 103 (44e1099c): 48038000.mcasp (GPIO UNCLAIMED) function mcasp0_pins group mcasp0_pins pin 104 (44e109a0): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 105 (44e109a4): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 106 (44e109a8): 48038000.mcasp (GPIO UNCLAIMED) function mcasp0_pins group mcasp0_pins pin 107 (44e109ac): 48038000.mcasp (GPIO UNCLAIMED) function mcasp0_pins group mcasp0_pins pin 108 (44e109b0): hdmi.12 (GPIO UNCLAIMED) function nxp_hdmi_bonelt_pins group nxp_hdmi_bonelt_pin s pin 109 (44e109b4): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 110 (44e109b8): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 111 (44e109bc): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 112 (44e109c0): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 113 (44e109c4): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 114 (44e109c8): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 115 (44e109cc): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 116 (44e109d0): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 117 (44e109d4): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 118 (44e109d8): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 119 (44e109dc): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 120 (44e109e0): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 121 (44e109e4): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 122 (44e109e8): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 123 (44e109ec): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 124 (44e109f0): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 125 (44e109f4): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 126 (44e109f8): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 127 (44e109fc): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 128 (44e10a00): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 129 (44e10a04): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 130 (44e10a08): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 131 (44e10a0c): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 132 (44e10a10): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 133 (44e10a14): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 134 (44e10a18): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 135 (44e10a1c): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 136 (44e10a20): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 137 (44e10a24): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 138 (44e10a28): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 139 (44e10a2c): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 140 (44e10a30): (MUX UNCLAIMED) (GPIO UNCLAIMED) pin 141 (44e10a34): (MUX UNCLAIMED) (GPIO UNCLAIMED) |
And a full list of the pins:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 |
root@beaglebone:/sys/kernel/debug/pinctrl/44e10800.pinmux# cat pins |more registered pins: 142 pin 0 (44e10800) 00000031 pinctrl-single pin 1 (44e10804) 00000031 pinctrl-single pin 2 (44e10808) 00000031 pinctrl-single pin 3 (44e1080c) 00000031 pinctrl-single pin 4 (44e10810) 00000031 pinctrl-single pin 5 (44e10814) 00000031 pinctrl-single pin 6 (44e10818) 00000031 pinctrl-single pin 7 (44e1081c) 00000031 pinctrl-single pin 8 (44e10820) 00000027 pinctrl-single pin 9 (44e10824) 00000027 pinctrl-single pin 10 (44e10828) 00000027 pinctrl-single pin 11 (44e1082c) 00000027 pinctrl-single pin 12 (44e10830) 00000027 pinctrl-single pin 13 (44e10834) 00000027 pinctrl-single pin 14 (44e10838) 00000027 pinctrl-single pin 15 (44e1083c) 00000027 pinctrl-single pin 16 (44e10840) 00000027 pinctrl-single pin 17 (44e10844) 00000027 pinctrl-single pin 18 (44e10848) 00000027 pinctrl-single pin 19 (44e1084c) 00000027 pinctrl-single pin 20 (44e10850) 00000017 pinctrl-single pin 21 (44e10854) 00000007 pinctrl-single pin 22 (44e10858) 00000017 pinctrl-single pin 23 (44e1085c) 00000007 pinctrl-single pin 24 (44e10860) 00000017 pinctrl-single pin 25 (44e10864) 00000027 pinctrl-single pin 26 (44e10868) 00000027 pinctrl-single pin 27 (44e1086c) 00000027 pinctrl-single pin 28 (44e10870) 00000037 pinctrl-single pin 29 (44e10874) 00000037 pinctrl-single pin 30 (44e10878) 00000037 pinctrl-single pin 31 (44e1087c) 00000037 pinctrl-single pin 32 (44e10880) 00000032 pinctrl-single pin 33 (44e10884) 00000032 pinctrl-single pin 34 (44e10888) 00000037 pinctrl-single pin 35 (44e1088c) 00000027 pinctrl-single pin 36 (44e10890) 00000037 pinctrl-single pin 37 (44e10894) 00000037 pinctrl-single pin 38 (44e10898) 00000037 pinctrl-single pin 39 (44e1089c) 00000037 pinctrl-single pin 40 (44e108a0) 00000008 pinctrl-single pin 41 (44e108a4) 00000008 pinctrl-single pin 42 (44e108a8) 00000008 pinctrl-single pin 43 (44e108ac) 00000008 pinctrl-single pin 44 (44e108b0) 00000008 pinctrl-single pin 45 (44e108b4) 00000008 pinctrl-single pin 46 (44e108b8) 00000008 pinctrl-single pin 47 (44e108bc) 00000008 pinctrl-single pin 48 (44e108c0) 00000008 pinctrl-single pin 49 (44e108c4) 00000008 pinctrl-single pin 50 (44e108c8) 00000008 pinctrl-single pin 51 (44e108cc) 00000008 pinctrl-single pin 52 (44e108d0) 00000008 pinctrl-single pin 53 (44e108d4) 00000008 pinctrl-single pin 54 (44e108d8) 00000008 pinctrl-single pin 55 (44e108dc) 00000008 pinctrl-single pin 56 (44e108e0) 00000000 pinctrl-single pin 57 (44e108e4) 00000000 pinctrl-single pin 58 (44e108e8) 00000000 pinctrl-single pin 59 (44e108ec) 00000000 pinctrl-single pin 60 (44e108f0) 00000030 pinctrl-single pin 61 (44e108f4) 00000030 pinctrl-single pin 62 (44e108f8) 00000030 pinctrl-single pin 63 (44e108fc) 00000030 pinctrl-single pin 64 (44e10900) 00000030 pinctrl-single pin 65 (44e10904) 00000030 pinctrl-single pin 66 (44e10908) 00000027 pinctrl-single pin 67 (44e1090c) 00000027 pinctrl-single pin 68 (44e10910) 00000020 pinctrl-single pin 69 (44e10914) 00000000 pinctrl-single pin 70 (44e10918) 00000020 pinctrl-single pin 71 (44e1091c) 00000000 pinctrl-single pin 72 (44e10920) 00000000 pinctrl-single pin 73 (44e10924) 00000000 pinctrl-single pin 74 (44e10928) 00000000 pinctrl-single pin 75 (44e1092c) 00000020 pinctrl-single pin 76 (44e10930) 00000020 pinctrl-single pin 77 (44e10934) 00000020 pinctrl-single pin 78 (44e10938) 00000020 pinctrl-single pin 79 (44e1093c) 00000020 pinctrl-single pin 80 (44e10940) 00000020 pinctrl-single pin 81 (44e10944) 00000027 pinctrl-single pin 82 (44e10948) 00000030 pinctrl-single pin 83 (44e1094c) 00000010 pinctrl-single pin 84 (44e10950) 00000037 pinctrl-single pin 85 (44e10954) 00000037 pinctrl-single pin 86 (44e10958) 00000062 pinctrl-single pin 87 (44e1095c) 00000062 pinctrl-single pin 88 (44e10960) 00000035 pinctrl-single pin 89 (44e10964) 00000027 pinctrl-single pin 90 (44e10968) 00000037 pinctrl-single pin 91 (44e1096c) 00000037 pinctrl-single pin 92 (44e10970) 00000030 pinctrl-single pin 93 (44e10974) 00000000 pinctrl-single pin 94 (44e10978) 00000073 pinctrl-single pin 95 (44e1097c) 00000073 pinctrl-single pin 96 (44e10980) 00000037 pinctrl-single pin 97 (44e10984) 00000037 pinctrl-single pin 98 (44e10988) 00000070 pinctrl-single pin 99 (44e1098c) 00000070 pinctrl-single pin 100 (44e10990) 00000000 pinctrl-single pin 101 (44e10994) 00000010 pinctrl-single pin 102 (44e10998) 00000027 pinctrl-single pin 103 (44e1099c) 00000002 pinctrl-single pin 104 (44e109a0) 00000024 pinctrl-single pin 105 (44e109a4) 00000027 pinctrl-single pin 106 (44e109a8) 0000001f pinctrl-single pin 107 (44e109ac) 00000030 pinctrl-single pin 108 (44e109b0) 00000003 pinctrl-single pin 109 (44e109b4) 00000027 pinctrl-single pin 110 (44e109b8) 00000030 pinctrl-single pin 111 (44e109bc) 00000028 pinctrl-single pin 112 (44e109c0) 00000030 pinctrl-single pin 113 (44e109c4) 00000028 pinctrl-single pin 114 (44e109c8) 00000028 pinctrl-single pin 115 (44e109cc) 00000028 pinctrl-single pin 116 (44e109d0) 00000030 pinctrl-single pin 117 (44e109d4) 00000030 pinctrl-single pin 118 (44e109d8) 00000030 pinctrl-single pin 119 (44e109dc) 00000030 pinctrl-single pin 120 (44e109e0) 00000020 pinctrl-single pin 121 (44e109e4) 00000030 pinctrl-single pin 122 (44e109e8) 00000030 pinctrl-single pin 123 (44e109ec) 00000028 pinctrl-single pin 124 (44e109f0) 00000028 pinctrl-single pin 125 (44e109f4) 00000028 pinctrl-single pin 126 (44e109f8) 00000030 pinctrl-single pin 127 (44e109fc) 00000028 pinctrl-single pin 128 (44e10a00) 00000028 pinctrl-single pin 129 (44e10a04) 00000020 pinctrl-single pin 130 (44e10a08) 00000028 pinctrl-single pin 131 (44e10a0c) 00000028 pinctrl-single pin 132 (44e10a10) 00000028 pinctrl-single pin 133 (44e10a14) 00000028 pinctrl-single pin 134 (44e10a18) 00000028 pinctrl-single pin 135 (44e10a1c) 00000020 pinctrl-single pin 136 (44e10a20) 00000028 pinctrl-single pin 137 (44e10a24) 00000028 pinctrl-single pin 138 (44e10a28) 00000028 pinctrl-single pin 139 (44e10a2c) 00000028 pinctrl-single pin 140 (44e10a30) 00000028 pinctrl-single pin 141 (44e10a34) 00000020 pinctrl-single |
Setting up the Circuit
Using the same circuit as in my old video. Since each GPIO module provides 32 dedicated GPIOs (general purpose input/output) and the GPIOs support 4 banks of 32 GPIOs (so, 128 GPIOs in total) the naming of GPIO0_5, would be GPIO 5 as (0 x32 + 5 = 5)
(Pin 12 on the P9 Header) GPIO1_28 – The LED = 1 x 32 + 28 = GPIO 60 (Offset 0x078, P9-12 GPIO1_28) #88
NOTE: GPIO 60 is not PIN 60!!!
If we check pins again and search for pin 60, by using the offset we can see:
1 2 |
root@beaglebone:/sys/kernel/debug/pinctrl/44e10800.pinmux# more pins |grep 878 pin 30 (44e10878) 00000030 pinctrl-single |
The pin mode on pin 30 is 30 HEX. What does that mean?
Well to understand this you need the document to beat all documents – the AM3359 Technical Reference Manual. http://www.ti.com/product/am3359 and you can see the link for this document. The version I am using is called the “AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (Rev.H). It is a 18.5MB document with 4,727 pages (no typo there – 4,700 pages!). The current direct link is: http://www.ti.com/lit/ug/spruh73j/spruh73j.pdf
The GPIOs section is Chapter 25 and begins on page 4,056. The page I am most interested in is Page 815, Section 9.3.51. You can search the PDF for “conf_<module>” if you are using a different version of the document.
The value: 0x30 Hex is 110000 in Binary, so what does that mean?
Well, you have to see the table:
Bit | Field | Reset | Description |
---|---|---|---|
6 | conf_<module>_<pin>_slewctrl | X | Slew Control. Slew Rate: Fast is 0, Slow is 1 |
5 | conf_<module>_<pin>_rxactive | 1h | Receiver Active. Input Enable: Receiver Disable 0, Receiver Enable 1 |
4 | conf_<module>_<pin>_putypesel | X | Pad Pullup/Pulldown Type. Pulldown is 0, Pullup is 1 |
3 | conf_<module>_<pin>_puden | X | Pad Pullup/Pulldown enable. Enabled is 0, Disabled is 1 |
2-0 | conf_<module>_<pin>_mmode | X | Mode. Pad functional mux select. A number between 0 and 7 i.e. 000 and 111. This depends on which mode we require. |
Well if you look at this table, you see that 0x30 means the slew rate is fast, the receiver is enabled, the pad is set for pullup and pullup is enabled. The Mode is 0. which means when you look a the table for this pin on the P9 header (Table 8. Expansion Header P9 Pinout), you see that pin is set as:
Beaglebone P9 Header, Pin 12, Mode 0 is gpmc_be1n, we would like to set it to Mode 7, which is gpio1[28] (Note the LED is currently on).
27 means 100111 = Fast, Enable Receiver, Pulldown type, enabled, mux mode 7.
37 means 110111 = Fast, Enable Receiver, Pullup type, enabled, mux mode 7.
Be careful, not all pins work in this way and there are external resistors on the board that affect the behaviour. For example, pins GPIO2_6 to GPIO2_14 all have external 42.2k resistors to GND and 100k resistors to high.
We can export the pins by echoing the GPIO number to /sys/class/gpio/export
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 |
root@beaglebone:/sys/class/gpio# ls -al total 0 drwxr-xr-x 2 root root 0 Jan 1 2000 . drwxr-xr-x 48 root root 0 Jan 1 2000 .. --w------- 1 root root 4096 Jun 1 22:21 export lrwxrwxrwx 1 root root 0 Jan 1 2000 gpiochip0 -> ../../devices/virtual/gpio/gpiochip0 lrwxrwxrwx 1 root root 0 Jan 1 2000 gpiochip32 -> ../../devices/virtual/gpio/gpiochip32 lrwxrwxrwx 1 root root 0 Jan 1 2000 gpiochip64 -> ../../devices/virtual/gpio/gpiochip64 lrwxrwxrwx 1 root root 0 Jan 1 2000 gpiochip96 -> ../../devices/virtual/gpio/gpiochip96 --w------- 1 root root 4096 Jan 1 2000 unexport root@beaglebone:/sys/class/gpio# echo 117 > export root@beaglebone:/sys/class/gpio# echo 60 > export root@beaglebone:/sys/class/gpio# ls -al total 0 drwxr-xr-x 2 root root 0 Jan 1 2000 . drwxr-xr-x 48 root root 0 Jan 1 2000 .. --w------- 1 root root 4096 Jun 1 22:22 export lrwxrwxrwx 1 root root 0 Jun 1 22:22 gpio117 -> ../../devices/virtual/gpio/gpio117 lrwxrwxrwx 1 root root 0 Jun 1 22:22 gpio60 -> ../../devices/virtual/gpio/gpio60 lrwxrwxrwx 1 root root 0 Jan 1 2000 gpiochip0 -> ../../devices/virtual/gpio/gpiochip0 lrwxrwxrwx 1 root root 0 Jan 1 2000 gpiochip32 -> ../../devices/virtual/gpio/gpiochip32 lrwxrwxrwx 1 root root 0 Jan 1 2000 gpiochip64 -> ../../devices/virtual/gpio/gpiochip64 lrwxrwxrwx 1 root root 0 Jan 1 2000 gpiochip96 -> ../../devices/virtual/gpio/gpiochip96 --w------- 1 root root 4096 Jan 1 2000 unexport root@beaglebone:/sys/class/gpio# cd gpio60 root@beaglebone:/sys/class/gpio/gpio60# ls -al total 0 drwxr-xr-x 3 root root 0 Jun 1 22:22 . drwxr-xr-x 8 root root 0 Jan 1 2000 .. -rw-r--r-- 1 root root 4096 Jun 1 22:24 active_low -rw-r--r-- 1 root root 4096 Jun 1 22:24 direction -rw-r--r-- 1 root root 4096 Jun 1 22:24 edge drwxr-xr-x 2 root root 0 Jun 1 22:24 power lrwxrwxrwx 1 root root 0 Jun 1 22:24 subsystem -> ../../../../class/gpio -rw-r--r-- 1 root root 4096 Jun 1 22:22 uevent -rw-r--r-- 1 root root 4096 Jun 1 22:24 value root@beaglebone:/sys/class/gpio/gpio60# echo "out" > direction root@beaglebone:/sys/class/gpio/gpio60# cat direction out root@beaglebone:/sys/class/gpio/gpio60# echo 0 > value root@beaglebone:/sys/class/gpio/gpio60# echo 1 > value root@beaglebone:/sys/class/gpio/gpio60# echo 0 > value root@beaglebone:/sys/class/gpio/gpio60# echo 1 > value |
Light goes on and off.
The Beaglebone Black System Reference Manual (SRM) is available at: http://circuitco.com/support/index.php?title=BeagleBoneBlack
Page 65 of the SRM has the table that you need to map the GPIO to the Offset!
GPIO1_28 maps to P9-12 with an offset of 160 (pin 88 44e10960)
Setup for Device Tree Overlays
https://github.com/jadonk/validation-scripts/blob/master/test-capemgr/README.md
As is described in this guide:
1 2 |
root@beaglebone:/lib/firmware# export SLOTS=/sys/devices/bone_capemgr.9/slots root@beaglebone:/lib/firmware# export PINS=/sys/kernel/debug/pinctrl/44e10800.pinmux/pins |
We now have $SLOTS and $PINS that we can echo
1 2 3 4 |
root@beaglebone:/lib/firmware# echo $SLOTS /sys/devices/bone_capemgr.9/slots root@beaglebone:/lib/firmware# echo $PINS /sys/kernel/debug/pinctrl/44e10800.pinmux/pins |
But we can also cat these values, for example cat $SLOTS:
1 2 3 4 5 6 7 |
root@beaglebone:~/temp# cat $SLOTS 0: 54:PF--- 1: 55:PF--- 2: 56:PF--- 3: 57:PF--- 4: ff:P-O-L Bone-LT-eMMC-2G,00A0,Texas Instrument,BB-BONE-EMMC-2G 5: ff:P-O-L Bone-Black-HDMI,00A0,Texas Instrument,BB-BONELT-HDMI |
Just so that I always have these environment variables I am adding them to my .profile. So my ~/.profile looks like this:
1 2 3 |
export SLOTS=/sys/devices/bone_capemgr.9/slots export PINS=/sys/kernel/debug/pinctrl/44e10800.pinmux/pins export CURL_CA_BUNDLE=/etc/ssl/certs/ca-certificates.crt |
Which includes the environment variable to set up the certs to fix the configuration issue for curl as discussed here: Git and Curl SSL Certificates Configuration on Beaglebone Black
If we wish to set these values now, without typing them twice we can use the ‘.’ so:
1 2 3 |
root@beaglebone:~# . ~/.profile root@beaglebone:~# echo $CURL_CA_BUNDLE /etc/ssl/certs/ca-certificates.crt |
And you can see that the variables have been set.
Using an Overlay
Overlays allow the initial device tree that was described at boot to be modified in userspace at run time. This is useful as we are able to enable any device without having to recompile the kernel and/or reboot. When you enable output using the pinmux settings, you’re only enabling the output driver circuitry at the pin. When you change the mux, you’re selecting which internal signal gets connected to this pins output driver. So, the pin mux (physical pin) is completely separate from the gpio block (internal signal). You have to enable both.
In this overlay example I am using the bone-pinmux-helper to enable the pins. The GPIO is treated as a separate peripheral, just like all other peripherals.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 |
root@beaglebone:~/boneDeviceTree/overlay# ls -al total 16 drwxr-xr-x 2 root root 4096 Jun 6 23:59 . drwxr-xr-x 6 root root 4096 Jan 1 2000 .. -rw-r--r-- 1 root root 1129 Jun 6 23:56 DM-GPIO-Test.dts -rwxr-xr-x 1 root root 124 Jun 6 23:29 build root@beaglebone:~/boneDeviceTree/overlay# more ./build #!/bin/bash echo "Compiling the overlay from .dts to .dtbo" dtc -O dtb -o DM-GPIO-Test-00A0.dtbo -b 0 -@ DM-GPIO-Test.dts root@beaglebone:~/boneDeviceTree/overlay# ./build Compiling the overlay from .dts to .dtbo root@beaglebone:~/boneDeviceTree/overlay# ls -al total 20 drwxr-xr-x 2 root root 4096 Jun 6 23:59 . drwxr-xr-x 6 root root 4096 Jan 1 2000 .. -rw-r--r-- 1 root root 952 Jun 6 23:59 DM-GPIO-Test-00A0.dtbo -rw-r--r-- 1 root root 1129 Jun 6 23:56 DM-GPIO-Test.dts -rwxr-xr-x 1 root root 124 Jun 6 23:29 build root@beaglebone:~/boneDeviceTree/overlay# cp DM-GPIO-Test-00A0.dtbo /lib/firmware |
Now, note when you echo DM-GPIO-Test > $SLOTS, make sure that you don’t pass DM-GPIO-Test-00A0.dtbo
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
root@beaglebone:~# cd /lib/firmware/ root@beaglebone:/lib/firmware# cat $SLOTS 0: 54:PF--- 1: 55:PF--- 2: 56:PF--- 3: 57:PF--- 4: ff:P-O-L Bone-LT-eMMC-2G,00A0,Texas Instrument,BB-BONE-EMMC-2G 5: ff:P-O-L Bone-Black-HDMI,00A0,Texas Instrument,BB-BONELT-HDMI root@beaglebone:/lib/firmware# echo DM-GPIO-Test > $SLOTS root@beaglebone:/lib/firmware# cat $SLOTS 0: 54:PF--- 1: 55:PF--- 2: 56:PF--- 3: 57:PF--- 4: ff:P-O-L Bone-LT-eMMC-2G,00A0,Texas Instrument,BB-BONE-EMMC-2G 5: ff:P-O-L Bone-Black-HDMI,00A0,Texas Instrument,BB-BONELT-HDMI 6: ff:P-O-L Override Board Name,00A0,Override Manuf,DM-GPIO-Test root@beaglebone:/lib/firmware# |
Checking the pins (for example, pins 88 and 85):
1 2 3 4 5 |
root@beaglebone:/lib/firmware# cat $PINS |grep 960 pin 88 (44e10960) 00000007 pinctrl-single root@beaglebone:/lib/firmware# cat $PINS |grep 954 pin 85 (44e10954) 00000027 pinctrl-single root@beaglebone:/lib/firmware# |
1020 is a20 – remember that it is in hexadecimal.
Now if we type dmesg, we can see the impact of this operation:
1 2 3 4 5 6 7 8 9 |
[ 62.334146] bone-capemgr bone_capemgr.9: part_number 'DM-GPIO-Test', version 'N/A' [ 62.334223] bone-capemgr bone_capemgr.9: slot #6: generic override [ 62.334242] bone-capemgr bone_capemgr.9: bone: Using override eeprom data at slot 6 [ 62.334260] bone-capemgr bone_capemgr.9: slot #6: 'Override Board Name,00A0,Override Manuf,DM-GPIO-Test' [ 62.334363] bone-capemgr bone_capemgr.9: slot #6: Requesting part number/version based 'DM-GPIO-Test-00A0.dtbo [ 62.334381] bone-capemgr bone_capemgr.9: slot #6: Requesting firmware 'DM-GPIO-Test-00A0.dtbo' for board-name 'Override Board Name', version '00A0' [ 62.338787] bone-capemgr bone_capemgr.9: slot #6: dtbo 'DM-GPIO-Test-00A0.dtbo' loaded; converting to live tree [ 62.338970] bone-capemgr bone_capemgr.9: slot #6: #2 overlays [ 62.342899] bone-capemgr bone_capemgr.9: slot #6: Applied #2 overlays. |
Now we can work with the GPIOs directly:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 |
root@beaglebone:/sys/class/gpio# echo 60 > export root@beaglebone:/sys/class/gpio# echo 49 > export root@beaglebone:/sys/class/gpio# ls -al total 0 drwxr-xr-x 2 root root 0 Jan 1 2000 . drwxr-xr-x 48 root root 0 Jan 1 2000 .. --w------- 1 root root 4096 Jun 7 14:00 export lrwxrwxrwx 1 root root 0 Jun 7 14:00 gpio49 -> ../../devices/virtual/gpio/gpio49 lrwxrwxrwx 1 root root 0 Jun 7 14:00 gpio60 -> ../../devices/virtual/gpio/gpio60 lrwxrwxrwx 1 root root 0 Jan 1 2000 gpiochip0 -> ../../devices/virtual/gpio/gpiochip0 lrwxrwxrwx 1 root root 0 Jan 1 2000 gpiochip32 -> ../../devices/virtual/gpio/gpiochip32 lrwxrwxrwx 1 root root 0 Jan 1 2000 gpiochip64 -> ../../devices/virtual/gpio/gpiochip64 lrwxrwxrwx 1 root root 0 Jan 1 2000 gpiochip96 -> ../../devices/virtual/gpio/gpiochip96 --w------- 1 root root 4096 Jan 1 2000 unexport root@beaglebone:/sys/class/gpio# cd gpio49 root@beaglebone:/sys/class/gpio/gpio49# ls active_low direction edge power subsystem uevent value root@beaglebone:/sys/class/gpio/gpio49# echo "in" > direction root@beaglebone:/sys/class/gpio/gpio49# cat direction in root@beaglebone:/sys/class/gpio/gpio49# cat value 0 root@beaglebone:/sys/class/gpio/gpio49# cat value 0 root@beaglebone:/sys/class/gpio/gpio49# cat value 0 root@beaglebone:/sys/class/gpio/gpio49# cat value 0 root@beaglebone:/sys/class/gpio/gpio49# cat value 1 root@beaglebone:/sys/class/gpio/gpio49# cat value 1 root@beaglebone:/sys/class/gpio/gpio49# cat value 1 root@beaglebone:/sys/class/gpio/gpio49# cat value 0 root@beaglebone:/sys/class/gpio/gpio49# cat value 0 root@beaglebone:/sys/class/gpio/gpio49# |
All is in order.
The C++ Code
All of the C++ code is available in the gpio directory of the github repository. The description of this code and its use can be found in the video.
Citation
If you use this video in your research, please cite:
Molloy, D. [DerekMolloyDCU]. (2012, May, 3). Beaglebone: GPIO Programming on ARM Embedded Linux [Video file]. Retrieved from http://www.youtube.com/watch?v=SaIpz0…
Further Reading:
Understanding the GPIOs: https://www.kernel.org/doc/Documentation/gpio/gpio.txt
Understanding Overlays: https://github.com/jadonk/validation-scripts/blob/master/test-capemgr/README.md
Understanding the Device Tree: http://devicetree.org/Device_Tree_Usage
I think this will be most helpful video for us in BBB. Especially on Device Tree in Linux.
Thanks for Your effort again.
amazing you did it, Thanks a lot
i will try in my BB with new image.
I followed all the instructions and it worked for me. In my BBB I have bone_capemgr.8 instead of bone_capemgr.9. Thanks a lot!
Célio Goetten
Brazil
When I follow one of the steps I get message:
root@beaglebone:~/boneDeviceTree/overlay# ls -l
total 16
-rw-rw-r– 1 root root 976 Jun 11 2013 DM-GPIO-Test-00A0.dtbo
-rw-rw-r– 1 root root 1844 Jun 11 2013 DM-GPIO-Test.dts
-rw-rw-r– 1 root root 1573 Jun 11 2013 DM-GPIO-Test.dts~
-rwxr-xr-x 1 root root 124 Jun 11 2013 build
root@beaglebone:~/boneDeviceTree/overlay# ./build
Compiling the overlay from .dts to .dtbo
Error: DM-GPIO-Test.dts:35.1-3 syntax error
FATAL ERROR: Unable to parse input tree
root@beaglebone:~/boneDeviceTree/overlay#
Really thank you for your help.
Marcin
Hi Marcin, I have seen this before when I downloaded the files to my PC and SFTP’d them across to the Beaglebone. I’m not sure why this happened as my transfer format was correct. The way I fixed this was to git clone directly to the Beaglebone and it worked perfectly. I don’t know if this is why you are having the problem. Derek.
Hi Derek,
I am working with interruption with the BBB and I am in need of a interruption @ 100 Khz. I am having problems with the polling. When I put more than 10 Khz the over load in the processor goes to 90%. I tried to use the GPIO-Keys driver and the Device Tree configuration to try not overload the processor, but seams that the GPIO-keys driver only work with interruptions less than 1Khz. I will try to use the PRU as a last resource.
I Wanna to say too that you website is one of the best that I saw!!!
Thanks.
So far without success in getting interruption @100 kHz without overload the CPU, do you have some idea about that?
Thanks.
Hi,
When I try to run build file. I have this problem. Can you help me?
Compiling the overlay from .dts to .dtbo
dtc: invalid option — ‘@’
Usage:
dtc [options]
Options:
-h
This help text
-q
Quiet: -q suppress warnings, -qq errors, -qqq all
-I
Input formats are:
dts – device tree source text
dtb – device tree blob
fs – /proc/device-tree style directory
-o
-O
Output formats are:
dts – device tree source text
dtb – device tree blob
asm – assembler source
-V
Blob version to produce, defaults to 17 (relevant for dtb
and asm output only)
-d
-R
Make space for reserve map entries (relevant for
dtb and asm output only)
-S
Make the blob at least long (extra space)
-p
Add padding to the blob of long (extra space)
-b
Set the physical boot cpu
-f
Force – try to produce output even if the input tree has errors
-s
Sort nodes and properties before outputting (only useful for
comparing trees)
-v
Print DTC version and exit
-H
phandle formats are:
legacy – “linux,phandle” properties only
epapr – “phandle” properties only
both – Both “linux,phandle” and “phandle” properties
Tarik, your post is kinda old, so I don’t know if you solved the issue already, but, I had the same issue and I solved using the post from: http://www.embedded-things.com/bbb/patching-the-device-tree-compiler-for-ubuntu/ hope this helps you or someone else!
leowise
Hello,
How can i kill Override Board Name,00A0,Override Manuf,DM-GPIO-Test. ( excluding reboot )
Amazing tutorial!
Thank you very much!
Hi Derek, I’m new to linux and Ran into problem when trying to./build ran into input/output error, so I try removing the input gpio 15 and while loop in vim, but its a read only file. How do I edit your C++ code and why would i get input/output error when trying to ./build?
I reset ubuntu and BBB then tried ./build and it works. I get bugged log in screens on USB over network a lot… BB seems buggy. What is the easiest way to Start editing the example you uploaded?
PS: I would love to see datalogger example video.
Hi Derek and friends, I have been trying to follow along with video for several days now and each time I get stuck in the same place. When I try to compile the DM-GPIO-Test.dts file I get an the followint error:
Error: DM-GPIO-Test.dts:35.1-3 syntax error
FATAL ERROR: Unable to parse input tree
I know I’m not the first to report this problem but after reading comments and trying the solutions posted on this site and on the Beagleboard forum site, I am totally stumped. I have used git to clone the pertinent files directly on the BBB; I have removed all comments from the first fragment; I have tried keyboarding the code by hand into a duplicate file to eliminate any invisible character. Still, I get the same error.
Does anyone have any suggestions?
Thanks, Peter M
BBB
uname -a
Linux beaglebone 3.8.13 #1 SMP Tue Jun 18 02:11:09 EDT 2013 armv7l GNU/Linux
Angstrom 6/20
I removed most of the comments in order to get the file to compile.
I appreciate your suggestion. I have tried removing comments in a previous attempt. I will try once more.
Thanks again,
Peter M
Hi Peter. I have no idea why this is. Stripping out the comments seems to work for most people, but it appears to me that dtc is being very fussy with syntax. Try retyping an almost empty dts using vi and see if you can get that to compile (e.g. one with just an include), then start adding until you get the error. Derek.
Hi Derek,
Thanks for your response and thanks for your lucid and inspiring videos and blogs.
I am a newbie on the beaglebone and mostly new on Linux but very interested and motivated. I will keep trying to write a dts file that will compile. I tried removing all comments; that didn’t work. I earlier tried writing from scratch, your dts file from this video resulting in the same error message. The error message points, I think the the section beginning with the line, “<<<<<<< HEAD". Can this section be changed to avoid the syntax error?
Again, thanks for your help,
Peter M
Hi Peter, That shouldn’t be there at all!! That’s a git update issue. You can manually remove all of the lines below:
<<<<<<< HEAD /* OUTPUT GPIO(mode7) 0x07 pullup, 0x17 pulldown, 0x0f no pullup/down */ /* INPUT GPIO(mode7) 0x27 pullup, 0x37 pulldown, 0x2f no pullup/down */ ======= /* INPUT GPIO(mode7) 0x07 pulldown, 0x17 pullup, 0x?f no pullup/down */ /* OUTPUT GPIO(mode7) 0x27 pulldown, 0x37 pullup, 0x?f no pullup/down */ >>>>>>> f83cf685371044f2fbc8e8da09759bed24038367
I will fix that later. Thanks for pointing that out!
Derek.
Hi Derek,
Deleting those line worked! The file compiled without complaint. I will now move on with my education. Y
Thanks for your videos and blog posts on the Beaglebone and thanks for your help.
Peter M
Only a question:
Could it be possible the overlays in addresses to put in structs together joined in a bbb.h – file to alias the addresses?
examples should be the stm32fxxx.h – file:
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x24-0x28 */
} GPIO_TypeDef;
and then wirte
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource4, GPIO_AF_FSMC);
…..
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
…..
GPIO_Init(GPIOD, &GPIO_InitStructure);
I am sorry I am new to this.
Pls could help i cannot locate the Directory ~/boneDeviceTree
sco
You need to clone my git repository into your directory, so in my case I cloned it to my home directory, which is always ~/ – it is equivalent in my case to saying /home/molloyd/ which contains the directory after git cloning of /home/molloyd/boneDeviceTree
Hi, Derek,
Great tutorial, thanks! Your whole website is fabulous!
Have you looked into reading the analog inputs of the Beaglebone Black?
Using
echo cape-bone-iio > $SLOTS
cat /sys/devices/ocp.2/helper.1*/AIN1
doesn’t work very well according to my multimeter. It seems like there may be issues in the ADC drivers.
It would be great if you could share your experience on this topic. Thanks so much!
Daniele
This is a great tutorial for a beginner like me. I have had limited success but am stuck on getting a reading from a ds18b20. I am trying to use p9 pin 12. But is it offset 160 or 0x078
From above:
Pin 12 on the P9 Header) GPIO1_28 – The LED = 1 x 32 + 28 = GPIO 60 (Offset 0×078, P9-12 GPIO1_28) #88
From not so far above:
GPIO1_28 maps to P9-12 with an offset of 160 (pin 88 44e10960)
From the PDF:
P9_12 30 0x878/078 GPIO1_28 60 gpio1[28]
From the BBB SRM A52 Table 11 P9 Pinout
12 U18 GPIO1_28 gpmc_be1n mii2_col gpmc_csn6 mmc2_dat3 gpmc_dir mcasp0_aclkr_mux3 gpio1[28]
And table 15 on page 90 of SRM
160 P9-12 GPIO1_28
Hi Ken,
P12 on the P9 Header in Mode7 is GPIO1_28 = GPIO 60 as you have said.
This is at address 44e10878 and offset 0x078 according to my table. A few values in the SRM did not work for me and this may have been one of them. Hence, I generated the table directly from the board itself.
Let me know if you get it working against my values,
Derek.
Yes, I have been able to flash the led and read the button according to your offsets. Even your TestApplication worked right out of the box. Offset 160 is pin 88 but I am not sure what it is used for yet or where it is on the headers. P9_12 is definitely at 078. Thanks for your great instruction.
Ken Klein
Lexington, KY
Hey Derek,
Really great video cheers – I was wondering how easy it would be to demonstrate an interrupt coming in from S2? I know it’s used by the HDMI (or so it seems) but would love to see how to use it from device tree through to a kernel module/user space.
Cheers, Nick
Is there a way to unload an overlay from the capemgr?
Loading an overlay is simple, but how to unload one ?
Thanks
# A=
perl -pe 's/^.*(\d+):.*/$1/' $SLOTS | tail -1
# echo “-$A”
-6
# echo “-$A” > $SLOTS
I found this code on another page. And it works^^ yet i don’t realy understand what it´s doing…
A is a variable and contains the value 6 … to remove overlay on slot 6
if i write -6 directly into slots (echo -6 > slots) my terminal shutdown…
Why?
Thanks
Thank you for the video, and the other videos.
Now the DM-GPIO-Test works.
The primary problem is that the “main-line” Device Tree Compiler does not handle overlays, or at least the -@ option and you have to either patch the source of the DTC or find a version that has been properly patched. Before hitting you head against the wall type ‘dtc -h’ and look for ‘-@’ as one of the permitted options. If there is no ‘-@’ option listed, the dtc will not work and will complain that input cannot be parsed and ‘@’ is an invalid option.
Tried downloading a version of dtc from RobertCNelson’s github repository. At work, it would not download because of proxy/firewall. When I tried it at home, without any proxy, it worked just fine.
How can configure and use its UART feature?
Hello Derek,
I want to change the mode settings of P9-17 and P9-18 pin which are 00000062 default. And I want to use that pins as normal pins. How can I change the mode of this pins permanentely.
Thanking you.
What would you need to do in order to do the Stepper motor with this new device-tree setup?
I tried doing it but it doesn’t seem to work.
My first attempt with custom .dts was this
0x034 0x2f /* P8_11 45 INPUT fast,RX enabled,PD/off,mode 7 */
0x030 0x2f /* P8_12 44 INPUT fast,RX enabled,PD/off,mode 7 */
0x028 0x2f /* P8_14 26 INPUT fast,RX enabled,PD/off,mode 7 */
0x03c 0x2f /* P8_15 47 INPUT fast,RX enabled,PD/off,mode 7 */
0x038 0x2f /* P8_16 46 INPUT fast,RX enabled,PD/off,mode 7 */
I really wasn’t sure what RX enabled/pullup/down should be
But when I did this then made slight change to your easy driver code(getting rid of omap_mux calls)
nothing would happen…
I even tried changing the .dts pins to 0x07 and that didn’t seem to do anything as well. Any tips would be appreciated
The line “Well if you look at this table, you see that 0×30 means the slew rate is fast,” just below the first table, does not match the value in the table.
Just being picky. Thanks for the great job. 🙂
I have a quick question regarding some of the “Real Time” functions of the AM335x on the BeagleBone Black. In the manual I see the following:
“The Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) is separate
from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility”
I have a process that while not “PROFIBUS” it is Modbus, and I would like to try and use the “Real Time” features. Do Device Tree Overlays make use of this or is this a special function that requires explicit definitions?
Have you made use of the independent sub-processes, and if so do you have any advice?
According to BBB user manual p61 and BBB schematic:
led user0 is connected on PIN GPIO1_21, so his pin number should be 1*32+21=53.
But in arch/arm/mach-omap2/board-omap3beagle.c his number is 150, and led user1 pin number is 149;
static struct gpio_led gpio_leds[] = {
{
.name = “beagleboard::usr0”,
.default_trigger = “heartbeat”,
.gpio = 150,
},
{
.name = “beagleboard::usr1”,
.default_trigger = “mmc0”,
.gpio = 149,
},
[…]
};
Do you have any explanation?
Hi, first of all, Mr Melloy, thank you for your implication and your creations !
I’ve a problem to change the mux of pin P9_17 and maybe someone can help me.
I used the file on the tutorial, (DM-GPIO-Test.dts) all if working for pin P9_17. I used the cape-bone-iio for analog, and the analog work fine. But when I try to mix both together, the pin P9_17 do not change to the good mode.
This is my DM-GPIO-Test.dts
http://ubuntuone.com/64pVz2qxo5PFUcLshrEVVO
I run on kernel 3.8.13, Beagle bone black. I’m stuck with this since 2 days, it’s probably a stupid error, but I can’t figure it out.
thank you
Julien
These are fantastic tutorials, and have saved me from throwing my BBB out the window and going back to the RPi! However, wouldn’t accessing IO using file open/close be really slow? Lets say if you were bit bashing a port. Just curious, is there no other way to do this?
from the article:
#————————–
Page 65 of the SRM has the table that you need to map the GPIO to the Offset!
GPIO1_28 maps to P9-12 with an offset of 160 (pin 88 44e10960)
#————————–
From the table, I can find out that P9-12 is mapped to GPIO1_28.
But….
How can I find out that P9-12(GPIO1_28) is mapped to Pin 88 in the list ?
Thanks.
Please ignore my above question. I think this was addressed by ken klein before and answered by the author..
Sorry for not reading all questions.
Thanks again for great tutorial.
Hello to all,
I try to solve a problem and can not do it:
root@ubuntu-armhf:/lib/firmware# echo DM-GPIO-Test > $SLOTS
bash: $SLOTS: ambiguous redirect
root@ubuntu-armhf:/lib/firmware#
the next step should be:
root@beaglebone:/lib/firmware# cat $SLOTS
0: 54:PF—
1: 55:PF—
2: 56:PF—
3: 57:PF—
4: ff:P-O-L Bone-LT-eMMC-2G,00A0,Texas Instrument,BB-BONE-EMMC-2G
5: ff:P-O-L Bone-Black-HDMI,00A0,Texas Instrument,BB-BONELT-HDMI
6: ff:P-O-L Override Board Name,00A0,Override Manuf,DM-GPIO-Test
I try to execute this command in different ways and i always get this as result: bash: $SLOTS: ambiguous redirect
Does anyone know how to solve this problem?
Thanks for your help
Hi,
can you explain what is active_low used for?
Does it invert all the bit coming into that pin?
Gustavo
Hello Dereck, your tutorial is awsome!! I have two questions:
1) In /sys/devices/ I got only “bone_capemgr.8” why?
2) I try to export the SLOTS and PINS, but I can´t to view .profile file. Why?
Thanks a lot!
Juan C.
One comment, you have a typo in the GPIO table for bit 4 “conf___putypesel” pullup is 1 and pulldown is 0.
Hi, I have the same problem, I can not find “.profile” I suppose that it is an file created for him but I don’t have idea how I can create it. Did you find how fix it?
Hi, yes if it doesn’t exist, just create a .profile file. Remember that you will have to do a ls -a to see hidden files (those with a . at the front). You can create it by using the nano editor e.g. nano .profile
Do you have a video or a tutorial on how to do ‘git’?
I’m hoping to get a beaglebone for christmas, but there’s so much I’m unfamiliar with! I have compiled a basic embedded hello world program for the beaglebone, but the electronics side and the source control side I’m still learning!
Hi Ben, I might do a full post, but as a short response, keeping it very simple you can follow these steps:
1) Create a new repository on the github.com website say username: gituser repository: temp Open Source Repositories are free.
2) On your local device – type “git clone https://github.com/gituser/temp.git”
3) Add your source code to that directory on your local device
4) When you are finished type “git add *” on the local device
5) Then you need to commit the changes, type “git commit -m “your message”” on the local device
6) Finally, push the code to the remote repository, type “git push”
Kind regards, Derek.
Hi
I have a problem that i cant seem to fix, i hope someone out there can give me some clues.
I have an LCD7 cape which when connected to the beaglebone loads the correct firmware into SLOT-0. I have swapped the LCD screen to one with a different resolution, so i have modified the BB-BONE-LCD7-01-00A3.dts firmware and recompilied this using the “dtc -O dtb -o BB-BONE-LCD7-01_00A3.dtbo -b 0 -@ BB-BONE-LCD7-01-00A3.dts” code provided by Derek. (this was all done in /lib/firmware directory).
However when the LCD7 cape is connected the old firmware is still loaded with the old resolution, even though i removed the original .dtbo file and replaced it, can anybody shed any light on this?
Is there another location firmware is located where the kernel could be reading the old .dtbo file?
Many thanks
Steve
`Derek,
I replicated your steps to enable PWMs. I was able to change the pin mode into PWM. How do i export PWM from /sys/class/pwm ? There is another method which uses echo am335x_pwm > $SLOTS and then you obtain the pwm directory structure in /sys/devices/ocp.3. This is a pre compiled overlay**.dtbo) file in lib/firmware
However I am more interested in knowing how to enable the PWM using a custom overlay, compiling it and then using it. Could you help with it.
I am using ubuntu 13.10 with 3.8.13 kernel
Derek,
I believe you have a mistake in this page.
In the table you flipped the PULLUP/DOWN SENSE.
Pullup should be 1 you have it as 0 and of course the PullDown goes with it.
Excellent write up though – thanks
Thanks for that. Fixed.
Hi Derek!
Did you mean pin 30 but not 60?
Sorry I did not study table P9 Now I understand your explanation
Hi Derek,
Thanks for the great tutorial. I also watched the video and that was great as well. I really appreciate it when someone goes through the effort of sharing knowledge in a well thought out and thorough way.
I’m hoping that you or someone can help me with my issue. I’m trying to make the BBB communicate with an RS-485 device using UART1 or UART4 through a breakout board that uses a max3485 transceiver. The issue that I have is that this unit requires RTS. All of the RTS pins are dedicated to other functions as your table clearly shows. I’ve made a custom overlay that I think would work, except the RTS and CTS pins conflict with either the I2C2 pins on UART1 or the HDMI pins on UART4.
How do I disable the I2C2 control of the P9_19 and P9_20 pins or the HDMI control of the P8_33 and P8_35 pins?
Do the following overlay changes look correct for UART1-RTS?
part-number = “BB-UART1-RTS”;
exclusive-use = “P9.26”, “P9.24”, “P9.20”, “P9.19”, “uart1”;
pinctrl-single,pins = ;
(Everything else is the same as the original BB-UART1.dts file)
Thank you, Tim
The previous post deleted the following snippet from the dts file snippet.
pinctrl-single,pins = ;
0x180 0x20 /* P9_26 = UART1_RXD, MODE0 */
0x184 0x00 /* P9_24 = UART1_TXD, MODE0 */
0x178 0x20 /* P9_20 = UART1_CTSN, MODE0 */
0x17c 0x00 /* P9_19 = UART1_RTSN, MODE0 */
I found a friend with an oscilloscope and we were able to find out part of the problem. We needed to connect TX-O on the 485 board to uart4_rx and RX-I on the 485 board to uart4_tx. You also need to disable the hdmi interface. Then the overlay found here: https://groups.google.com/forum/#!topic/beagleboard/6am1GKyo60s will sort of work. The remaining issues are:
1. The 485 board needs RTS to be low in order transmit and needs RTS to be low in order to receive. The uart4_rts pin is working opposite of this. Or perhaps I should say the 485 board is expecting the opposite signal from what the pin is giving it. How can I reverse the default polarity of the uart4_rts pin so it is low for transmit and high for receive?
2. I’m using pyserial and when I setup the serial port in pyserial: ser = serial.Serial(port = “/dev/ttyO4”, baudrate=9600, rtscts=True) it actually disables the RTS pin. Or at least it stops working in automatic mode. How I use pyserial with RTS?
How can I load the “6: ff:P-O-L Override Board Name,00A0,Override Manuf,DM-GPIO-Test” automatically when starting up?
Michael:
Assuming the DM-GPIO-00A0.dtbo file is in the /lib/firmware directory, edit /media/BEAGLEBONE/uEnv.txt so that it looks like
optargs=quiet drm.debug=7 capemgr.enable_partno=DM-GPIO
(should all be on one line). Reboot and cat /sys/devices/bone_capemgr.*/slots and you should see the overlay loaded.
Hi Derek,
I just compile a Yocto linux for BeagleBone Black using dora branch.
But in my distribution I cant see the path:
/sys/devices/bone_capemgr.9/slots
Do you know if there some to do for enable this feature (overlay in userspace)?
Thanks.
Hi Derek,
I tried to clone the code. I got error message. Please advise.
root@beaglebone:~# git clone git://github.com/derekmolloy/boneDeviceTree.git
Cloning into boneDeviceTree…
fatal: Unable to look up github.com (port 9418) (Name or service not known)
root@beaglebone:~#
Thanks,
-Feng
Hi Feng, that looks like a network problem. Can you ping 8.8.8.8? If so you have IP access and it is a nameserver problem. Can you ping http://www.google.com? If so, then I am at a loss. Is github blocked from your location? You should be able to go in using the web interface at the worst case using http://github.com/ Derek.
Hi Derek, Both don’t ping. It’s probably because I’m using USB to connect. I will download directly from HTTP then.
Thank you!
Great information, thank you. You’re a tremendous resource for the BBB community.
As of December, 2013, revision J of the AM335x Technical Reference Manual is the current version, so your direct link should now be (still reachable from the product page):
http://www.ti.com/lit/ug/spruh73j/spruh73j.pdf
Thanks Mike, Have updated the link, Derek.
Derek,
Thanks for your outstanding lecture. You have a wonderful flowing style with a fine balance of detail vs. getting on with the big picture.
Question:
I appreciate the pedagogical value of writing text to Linux files to accomplish I/O. But as an inveterate real-time graphics programmer I cringe at the inefficiency of this approach.
Is there some reason I can’t write directly to the BBB GPIO pin addresses once I take them away from the kernel with EXPORT?
Thanks russ. Yes for real-time programming this structure is not ideal. It is possible to flush the stream to avoid opening and closing each time, but if you need real-time performance then you will have to look at the PRUs. The real advantage of embedded Linux is the software support that it provides, but it is limited for real-time programming.
Hi, how can i control the pins between GPIO2_6 to GPIO2_14?
This is so needlessly complex it literally gave me a migraine trying to understand it.
This is such typical Linux nonsense.
One might say “but look at all the power you have,” to which I would reply “look at all the nonsense you have to fiddle with to write a ONE OR A ZERO out of a GPIO pin.”
It would be faster for me to buy a parallel port, install Windows XP, and write an application in assembler to bit-bang what I want out of the parallel port than it would to bother to comprehend this device tree nonsense.
It is no wonder people use Windows.
… someone get me some morphine. this hurts my head.
I completely agree – overly complicated because no one wants to pull their head from the trough of low level geek fodder and see the larger goal – I/O configuration. I really don’t care what a device tree overlay is and whether or not I have to use one to configure my pins. I simply want to configure my I/O to accommodate the circuit.
And here’s the best part. I’ve been thinking I’ll circumvent this pile of horse manure by creating a cape with an EEPROM that defines all the pin configurations. That’s great, plug in the hardware and auto-configure your I/O. But NO, you still need a DTO in addition to this which, for the life of me, I can’t see why.
Note: For anyone reading this, please do not respond to explain why – I’m not interested in how bad designs work, only good ones.
When you said:
“If we check pins again and search for pin 60, by using the offset we can see:”
Did you mean:
“If we check pins again and search for pin 30 (GPIO 60), by using the offset (0x078) we can see:”
Not sure if this was mentioned before, but the link to the Linux kernel GPIO docs is stale. The correct link is: https://www.kernel.org/doc/Documentation/gpio/gpio.txt
Hi Derek,
From ken klein’s comment & your reply above:
“Hi Ken,
P12 on the P9 Header in Mode7 is GPIO1_28 = GPIO 60 as you have said.
This is at address 44e10878 and offset 0×078 according to my table. A few values in the SRM did not work for me and this may have been one of them. Hence, I generated the table directly from the board itself.
Let me know if you get it working against my values,
Derek.”
I’m having trouble generating the GPIO mapping table from the board. The offsets in the SRM don’t work. Can you please let me know how you generate the mapping table from the board itself? That would be useful insight for me. Thank you in advance!
Regards,
Ashok R.
Hi Derek and friends,
Thanks for all discussion here. I am a new to linux world and followed every step as shown in the video. Good part is I could see change in mode for pins shown in video.
Now I want to change modes of lcd_data pins i.e. P8_31 to P8_46 as GPIO. When I insert addresses like 0x0a0, 0x0a4 etc in .dts file, I do not see any relevant changes in modes of these files when seen on $PINS | more.
Point to note is I followed same procedure again by deleting previous files. Also, mode changes are seen correct when pin addresses are changed to those demonstrated in video.
Is there any restriction in using lcd_data pins as GPIO (I am not using HDMI port)? or is there any other way to put Hex numbers as addresses?
My code in fragment 0 looks like this:
fragment@0 {
target = ;
__overlay__ {
pinctrl_test: DM_GPIO_Test_Pins {
pinctrl-single,pins = ;
code doesn’t work. But when i revert back to below code, everything works well.
fragment@0 {
target = ;
__overlay__ {
pinctrl_test: DM_GPIO_Test_Pins {
pinctrl-single,pins = ;
Can anyone comment on this?
I guess code was changed by site settings automatically. Hence, copying it again here.
Code which works:
0x078 0x07 /* P9_12 60 OUTPUT MODE7 – The LED Output */
0x184 0x2f /* P9_24 15 INPUT MODE7 none – The Button Input */
0x034 0x37 /* P8_11 45 INPUT MODE7 pullup – Yellow Wire */
0x030 0x27 /* P8_12 44 INPUT MODE7 pulldown – Green Wire */
0x024 0x2f /* P8_13 23 INPUT MODE7 none – White Wire */
/* OUTPUT GPIO(mode7) 0x07 pulldown, 0x17 pullup, 0x?f no pullup/down */
/* INPUT GPIO(mode7) 0x27 pulldown, 0x37 pullup, 0x?f no pullup/down */
Code which doesn’t work:
0x0a8 0x07 /* P8_43 72 OUTPUT MODE7 */
0x184 0x2f /* P9_24 15 INPUT MODE7 none – The Button Input */
0x034 0x37 /* P8_11 45 INPUT MODE7 pullup – Yellow Wire */
0x030 0x27 /* P8_12 44 INPUT MODE7 pulldown – Green Wire */
0x024 0x2f /* P8_13 23 INPUT MODE7 none – White Wire */
/* OUTPUT GPIO(mode7) 0x07 pulldown, 0x17 pullup, 0x?f no pullup/down */
/* INPUT GPIO(mode7) 0x27 pulldown, 0x37 pullup, 0x?f no pullup/down */
Hi Derek,
Just learning – thanks for the great write-up and video! Question: Can I be using both Mode 0 (for the SPI pins) and Mode 7 for a GPIO interrupt on another pin at the same time (the same Python program running)?
I was wondering because every so often my code freezes and I am guessing but maybe something gets confused as to which Mode the mux is in???
Thanks so much!
Hello,
I want to use the Pins P9_29 and P9_31 as PWM.
How do I disable these pins mcasp?
Thanks for this excellent tutorial Derek. This will really help get me started with the BBB. I have been searching for a few days on how to change the pin MUX etc.
Unloading and reloading an overlay doesn’t work. If I make an overlay following your example for a single pin, with a setting of 0x27 (input with pull-down enable), it works right after boot. Same for pull-up (0x37). But if
I try to unload the overlay (echo ‘-overlay_number’ >$SLOTS) and load one with the opposite pull setting it
doesn’t seem to take: I still get high if it was initially configured with pull-up, or low if initially configured with
pull-down.
Is there anything in the overlay example itself that might be causing this, or is it just a bug somewhere?
Hi Molloy,
I am using BBB with angstrom linux (Kernel 3.18.13)..I am following your instruction for gpio. I am not able to make it work.. I am getting the following error when i am echo-ing DM-GPIO-TEST to /sys/devices/bone_capemgr.9/slots.Any help?
error:
sh: echo: write error: No such file or directory
But slots file is present and i could read it..
Am I correct in assuming that all of the IO performed using the techniques explained here are using ‘polled’ techniques ‘behind-the-scenes’? Or is the kernel using interrupt service routines to drive IO?
Hi Derek, thank you very much for these tutorials, and the book (which I just bought, hoping it would help with my issue).
No matter what I do, I can’t get the GPIO inputs value to reflect the actual state of the pin. I tried one output and I couldn’t get the pin’s voltage to change despite changing the value. I’m running Debian 7/3.8.13-bone68. Everything I can think to check matches what you have on this page and in the book.
Even pins that are configured by default as input with pullup enabled report a value 0 (but checking with the DMM, the pin is near 3.3 V). I’ve tried pins on both headers.
FWIW, I’ve been able to use the ADC for some time.
Any idea on what I can check? Thank you!
Ah, I figured it out. I misunderstood all the admonitions that “GPIO number” wasn’t the same as “pin number.” I thought “GPIO Number” was some TI reference, and “pin number” was how Linux referred to the pin. But in fact, Linux (in its infinite wisdom) uses two different labels for a pin, depending on what part of sysfs you’re using. Awesome. Just awesome.
To be clear: The “pin number” (e.g. 36 for P8_07) is what’s used in /sys/kernel/debug/pinctrl/44e10800.pinmux/pins. The “GPIO number” is what’s used in /sys/class/gpio/… (e.g. 66 for P8_07).
Hi Rick, Yes, that issue has caught many people out (including me on my first pass!). I have listed the software reference as $PINS on the P8/P9 header tables. The book should help! — there is a big warning that makes that clear in Chapter 6 :-). Thanks for your support, Derek.
Hi everybody,
Thank to your explanation is now clear to me too.
But there is another problem in this site, which I cannot understand and I think it is a typo made by Mr. Molloy.
I refer to the fact, that at the very beginning of the page the used gpio is the following one:
Pin 12 on the P9 Header) GPIO1_28 – The LED = 1 x 32 + 28 = GPIO 60 (Offset 0x078, P9-12 GPIO1_28) #88
Mr. Molloy calculates the GPIO corresponding pin and then writes the offset for that port.
That’s ok, but lately in this page he wrote:
Page 65 of the SRM has the table that you need to map the GPIO to the Offset!
GPIO1_28 maps to P9-12 with an offset of 160 (pin 88 44e10960)
Despite of the fact that I couldn’t find any help at that page (but I found the checklist on page 104 of the SRM very helplful), the real problem is that I cannot understand why the GPIO1_28 has now 2 different offsets.
The former is 0x078 and latter is 160 (0x0A0 in HEX).
Which is the real offset of that pin?
Is a mistake in this website or there is another explanation?
Anyway this tutorial is really helpful and very interesting to understand the beaglebone.
Regards and happy new year.
Hello Derek, Thaks for the tutorial. After following it I was able to change the state of GPIO pins in userspace by exporting them. However I am writing a kernel module to write values to the GPIO pins however that does not work. My approach was to follow your procedure to configure the mux to set the corresponding pins to GPIO output. Then set the bits within my kernel module using GPIO registers
Hi Derek
I am using custom board based on AM335x and sdk-7 not beagle bone black board, we are not using HDMI controller and we direct interface leds to lcd_data0* to lcd_data7* pins(GPIO2_6,7,8,9,10,11,12) we took reference as bbb user leds.
1. In am33xx_pinmux: pinmux@44e10800
compatible = “gpio-leds”;
0xa0 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* lcd_data0.gpio2_6 D0/Away_LED shan */
0xa4, 0xa8,0xac… offset add etc
2. in leds node
led@6 {
label = “Away_led”;
gpios = ;
linux,default-trigger = “heartbeat”;
default-state = “on”;
};
3. shell prompt
root@am335x-evm:/# cd sys/class/leds/
Away_led/ beaglebone:green:usr2/
beaglebone:green:heartbeat/ beaglebone:green:usr3/
beaglebone:green:mmc0/
root@am335x-evm:/# cd sys/class/leds/Away_led
root@am335x-evm:/sys/class/leds/Away_led# ls
brightness max_brightness subsystem uevent
device power trigger
root@am335x-evm:/sys/class/leds/Away_led# echo 1 > brightness
root@am335x-evm:/sys/class/leds/Away_led# echo 0 > brightness
4. All commands are executed fine but am unable turn on leds here i am checking through sys/class/leds/ attributes like brightness and trigger, please give me any suggestion……
Thanks and Regards………
Hi Derek,
I believe there is a broken link under Further Reading. “https://www.kernel.org/doc/Documentation/gpio.txt” needs a “gpio” making it “https://www.kernel.org/doc/Documentation/gpio/gpio.txt”
Thanks Dennis, I fixed that.
Hi Dennis,
First off, great book and blog for the BBB, I am just getting started and it has be hugely helpful.
Apologies if this is redundant post, but it seems the DTO mechanism for updating the device trees at runtime has been removed from recent kernels (greater than 3.8 I believe). In particular, the /sys/devices/bone_capemgr.9 file is gone.
They are apparently working on something new but in the mean time do you have any suggestions? Should I revert back to the “onerous” mechanism of editing DTS directly and recompiling?
Thanks for any help,
– Steve
Hi Derek. Great info, love all your videos and your book.
I’ve got this to work as the root user, but how do you get it to work as a non-root user? For instance, the user “debian”. It does not have write access to the /sys/class/gpio directory.
I wrote some hack code to get around this using the system() command and sudo, but there must be a proper way.
An example of my hack:
// setDirection(INPUT):
ostringstream theCommand;
theCommand <” <path << "direction\"";
system(theCommand.str().c_str());
Hi,
I’m currently using a an ubuntu distribution -> https://rcn-ee.com/rootfs/2015-07-08/flasher/BBB-eMMC-flasher-ubuntu-14.04.2-console-armhf-2015-07-08-2gb.img.xz in my beaglebone black
In that version, there’s no folder /sys/devices/bone_capemgr.9, How do i load the dtbo files to configure the pins?
Thanks advanced!
Hello!
This works, but then i use analog inputs, in /sys/devices/bone_capemgr.*/slots we can see:
11: ff:P-O-L Override Board Name,00A0,Override Manuf,DM-GPIO-Test
12: ff:P-O-L Override Board Name,00A0,Override Manuf,cape-bone-iio
But gpio pinmux not changed.
Then i turn off cape-bone-iio, pinmux changes propertly. Any things?
Dear Derek thank you very much for your great tutorials. They are helping me a lot in my project.
Nevertheless, I am facing a problem of the cape manager. I have to unload an overlay that was already on my distribution, in order to load a custom overlay. But everytime I try to unload the specific overlay the BBB crashes and after a reboot nothing has changed. Disabling the overlay in the uEnv.txt doesnt help either. Can you help me please? Im very new to this environment..
Hi Derek
First of all many thanks for the very well organized tutorial. I learned a lot.
However, I am facing an issue when trying to load the newly created profile, i.e.
The command:
[prompt$] echo DM-GPIO-Test > $SLOTS
says an error did occur:
-su: echo: write error: Invalid argument
I can’t understand the reason for that and I would be glad if you can help.
My configuration seems to be ok. The following commands react correctly.
[prompt$] cat $SLOTS
0: PF—- -1
1: PF—- -1
2: PF—- -1
3: PF—- -1
[prompt$] ho BB-ADC > $SLOTS
[prompt$] cat $SLOTS
0: PF—- -1
1: PF—- -1
2: PF—- -1
3: PF—- -1
6: P-O-L- 0 Override Board Name,00A0,Override Manuf,BB-ADC
[prompt$] uname -a
Linux bbone1 4.1.12-ti-r29 #1 SMP PREEMPT Mon Nov 9 22:46:19 UTC 2015 armv7l GNU/Linux
In advance many thanks for your help.
Hi,
I just wanted to say “thank you” for these great tutorials. I have made an “arcade-in-a-stick” out of a Beaglebone black, and honestly I don’t know how I would have succeeded to code the controller without your great articles (this specific one was my Bible 🙂 ).
I have been documenting my project on a Blogger page, and I have just added links to your work. Thanks *a lot*.
Thanks Alban, great project and I love the final version — very professional!
hi,
i’m working on a project using the BBB , and i want to controle the BBB GPIO using NetBeans, it didn’t work , can u help in this issue please
best regards
Hi Derek! Thank you so much for the video! Very helpful and excellently done. Our project is integrating a Cirrus m5102 (SoC 6 channel ADC/sound) with the BBB.
best
Clark
What I have to do with a BeagleBoard xM?
Hi derek,
Thank you so much for these tutorials. They are a life saver.
I dont know if this post is related to this topic or not but I am having some trouble connecting a flight controller to the BBB.
I am trying to connect the KK Mini flight controller which takes in 4 PWM signals at 5 volts. I need to basically output 4 PWMs from the BBB at 3.3 V to the flight controller at 5 V. I have used a logic converter circuit using 4 N MOSFETs. The trouble is that these have damaged one BBB and I dont want to repeat that again. I think the problem is when the BBB is switched off these four wires going to the logic converter circuit are at 3.3V by default and this voltage going back to the BBB is destroying the board as it is mentioned in multiple places in the SRM that we should never give any voltage to the GPIO pins when the BBB is powered down. How do you suggest that I connect these circuits so that they are always powered on after the BBB finishes booting up and powered down before it switches off.
http://www.hobbytronics.co.uk/image/data/tutorial/mosfet_level_converter.jpg
This is the circuit that I have implemented. The low side is connected to the BBB and the high side is connected to inputs on the flight controller. Another thing I have tried is to give the +3.3V source from one of the GPIO(P9_23) instead of the 3V3 rail on the BBB so that I can control switching on and off the low side before the signal wires go high or low but this doesn’t seem to work as it doesn’t change the output signal when I change the input signal. But when I connect the voltage source to 3V3 it works. Could you suggest me a better option that I can use universally wherever I need to convert 3.3V to 5V for my signals(including the PWM).
Also I have discussed this question in further detail on stackexchange.
http://electronics.stackexchange.com/questions/239803/connecting-the-beaglebone-black-to-the-kk-mini-flight-controller/239807?noredirect=1#comment523325_239807
Please consider giving me some advice. It would greatly benefit the project.
Thanks,
Roy
Hi Derek..
Thank you so much for these tutorials. i am facing a problem.. i installed debian 8.4 in my emmc and ubuntu 16.04 in my sd card(external) when i connect seven segment display to the beaglebone black in which part ‘a’ of display connect to GPIO_48 but on echo it high or low in Ubuntu it cannot changes state remain off but in case of debian it changes can you please help me with this whats happening in my Ubuntu image? on reinstalling ubuntu does not make any changes problem remains
Hello,
I want to use the Pins P9_21 and P9_23 for a BUSY flag. For P9_21 it works. But for P9_23 it don’t work.
“P9.21”,
“P9.23”,
/* the hardware ip uses */
“gpio0_3”,
“gpio1_17”,
fragment@0 {
target = ;
__overlay__ {
bb_adcgpio_pins: pinmux_bb_adcgpio_pins {
pinctrl-single,pins = gpio3/ cat value i get “0” by default. But for >gpio49/ cat value I get by default “1” . Thats the problem.
I am trying to follow the example above for deployment of an overlay. Whether I follow the DM-GPIO-Test example or the example at https://github.com/jadonk/validation-scripts/blob/master/test-capemgr/README.md I get errors in dmesg that look like ….
pin 44e10964.0 already requested by ocp:P9_42_pinmux; cannot claim for ocp:helper
…..
could not request pin 89 (44e10964.0) from group pinctrl_test_7_pins on device pinctrl-single
….
etc.
Can you point me toward how to troubleshoot or correct this?
Thank you.
The path to the capemanager have changed to…
/sys/devices/platform/bone_capemgr/slots
…but even so, the GPIO device overlay seems to be broken. Attempts to load the overlay result in the following error message in dmesg…
bone-pinmux-helper: probe of ocp:helper failed with error -22
…and scrolling back though the logs, it looks like many standard loaded overlays fail during clean boot up as well.
I think the only choice in recent versions is to recompile a full DTC and load it at boot up. 🙁
in recent versions of the kernel, so now you would use…
echo PRU-GPIO-EXAMPLE >
Derek,
I really like your book. I’ve got a couple of Beagles (2GB and 4GB). I’ve been running the 2G from a 16GB MicroSD card.
john@beaglebone:~/dtb-rebuilder/src/arm$ lsb_release -a
No LSB modules are available.
Distributor ID: Debian
Description: Debian GNU/Linux 8.6 (jessie)
Release: 8.6
Codename: jessie
And kernel
Linux beaglebone 4.1.4-ti-r8 #1 SMP PREEMPT Thu Aug 6 21:01:16 UTC 2015 armv7l GNU/Linux
I’m ready to do an update to bring in the latest kernel
apt-get install linux-image-4.8.9-bone2 – Linux kernel, version 4.8.9-bone2
But I’m wondering if it’s worth it.Most of the literature out there is for Angstrom and Debian Wheezy. And hardware support for LCD displays seems to have stalled at Angsrom or at most Wheezy with QT.
In fact I’m wondering the Beaglebone is worth the effort anymore. That the Pi has finally become the VHS verses Betamax.
John
Hi Derek, first of all, thank you for the amazing content. Between the youtube videos and your book, I’m learning a lot. I have what I think should be a simple and quick question, bear with me as I’m a newbie with Linux. I’ve been going through all your example without any issues up until the device tree overlay. To this point I have spend quite sometime trying to figure out how to get it working with the latest Debian image (Jessie). I’m, as previous poster, have not been successful to change the pinmux state. Could you please share what version of Debian you where using when writing the book?
Found it, page 37 of your book. 3.8.13-bone67
Hi Derek,
Will you please explain me how to configure LORA (sx1272) on BBB using SPI for lora to lora communication.
Regards
Rohit
Hello Derek. Thank for great tutorials. I am new in embedded Linux and I have a problem with understanding Device tree overlay
I just need to change default state of the I2C pins ( P9.19 and P9.20) to GPIO mode. Is there quick path without be a PhD to do it
I think it will be useful for all users like me. Thanks in advance.
Great book Dr. Molloy. A question:
I spent the better part of a day learning to write a DTO to enable I2C1 on pins 17, 18. I put the .dtbo in the /lib/firmware and everything worked great when loading it into the slots…..THEN….
on page 280 of your book, you demonstrate how to enable I2C1 with a single line of code….certainly much quicker then learning to write a DTO….so my question is, what is happening here? i.e. Where does the “BB-I2C1” come from when you use the echo command…and what is it? is there some hidden DTO overlays that ship with the BBB somewhere to enable/mux these pins?
First, congratulations for your blog! Well, I have a doubt. In the video, it was presented one mode to set the pins at your own device tree cape. But if you made this in device tree, for example it was set P9_12 as output there, why you needed to set again in linux terminal this same gpio as output? Another question: what is the version of your Debian? Is make difference if I use the OS in emmc or sd-card? Regards, Eduardo Sousa.
Looks like the cape manager and associated slots file have gone away in favor of uboot overlays. Is there updated info for the above procedures that takes this into account and sets up the uEnv.txt file appropriately?
I love your book and I’m thrilled with the resources you’ve made available. You, and others like you, have allowed me to come a long way with little formal EE/CS training and it’s been a hell of a lot cheaper than my formal education.
I’m trying to use a beaglebone black to do some RS232 communication with an old CNC machine. I’ve currently got it working with software flow control by enabling one of the UARTS and then setting the parameters with stty -F commands such as:
stty -F /dev/ttyS1 4800 parenb cs7 -icrnl ixon nl1 cr1
I then copy the file I want to send to my CNC mill to the uart with a basic copy command such as:
cp ~/mydirectory/MyG_Code.nc /dev/ttyS1
all that works just fine.
What I’d like to do now is upgrade things a bit. I’d like to implement hardware flow control, and I think the BBB is capable of it, but I can’t seem to figure out how. Looking at various pinmuxing spreadsheets that people have put together I see for example that P9_19 and P9_20 are uart1_rtsn and uart1_ctsn respectively. I feel like I should be able to use these for hardware flow control in my project however when I ask the beaglebone what modes these pins can be configured to I don’t get rtsn or ctsn. For example:
config-pin -l P9_19
>>>>>>yields>>>>>>
default gpip gpio_pu gpio_pd gpio_input spi_cs can i2c pru_uart timer
Nowhere does it list RTS/CTS for any of the pins that are described in the pinmux spreadsheets of having RTS/CTS modes. Can anyone shed some light on this for me?
Thanks in advance
Hi Derek,
Thank you so much for these great videos, they have already helped me so much, I have one question. Early on when you use the command export SLOTS=/sys/devices/bone_capemgr.9/slots it appears as though it works, however, when I try cat $SLOTS the output is that there is no such file or directory. This is especially confusing to me, because when I export PINS and use cat, it works perfectly. If you could explain this, I would really appreciate it.
Thank you
Dear Derek,
I write to you because your blog is the most complete reference I have found out there, and because I think your solution is the closest to solving my problem.
I have a beaglebone for which I have gotten a LCD display-cape from newhaven (LCD7.0) and I have found out that newer linux images are less buggy to work with that cape.
The problem is that the newest linux does not allow me access the famous “/slots” file. If I do ‘more’ I see nothing, and if I write ‘cat’ I see a single hex character and nothing more.
For my plans I need to be able to activate the PWM pins, I have been visiting many sites on the internet looking for a solution but either I downgrade the linux-kernel and the LCD becomes buggy, or I find a way to access the “slots” files.
A third solution would be to know what is alternative is being offered now that the “slots” files is no longer accessible. Could you let me know if there is a reference to access PWM in newer linux versions?
Thank you for your time,
Gabriel
hi how are you?
when i want use overlay and compile it i have warning after use ./build in this directory(root@beaglebone:~/boneDeviceTree/overlay#)
warning is :
Compiling the overlay from .dts to .dtbo
DM-GPIO-Test-00A0.dtbo: Warning (unit_address_vs_reg): Node /fragment@0 has a unit name, but no reg property
DM-GPIO-Test-00A0.dtbo: Warning (unit_address_vs_reg): Node /fragment@1 has a unit name, but no reg property
Eduardo, you asked why you need to set P9_12 as an output in the device tree, and then again with the “echo out > … direction” command. I puzzled over this for a while too. The answer is tht the device tree sets the pin as an output, while the echo command sets the GPIO register bit as an output. Because pins have multiple uses, the pin’s direction can be different from the GPIO bit’s direction. But if they don’t match, the GPIO won’t work.
It took me a while to understand, that when you type “git clone https://github.com/gituser/temp.git”
the directory “temp” will be created in the directory in which you executed this command.
Linux version used: Debian 9.5 LXQT
I need to use S2 switch on the beaglebone black as GPIO. This S2 is connected to P8_43 (GPIO72 / P2_8) and by default used for HDMI.
In here as per my requirement I need to switch between GPIO to HDMI and HDMI to GPIO functionality at runtime. As device tree is loaded at u-boot level for my version of debian, this switching can happen at bootup.
How can i change this at runtime?
Please detail out the procedure along with device tree overlay, commands required.
I have tried Config-pin utility but it shows error saying pinmux is missing.
Please reply, Thanks in advance
Hi
I have a question about, though it is not related to Beaglebone board.
I have a board named ev-imx287-nano which is a PCIe core board. I am using RS485 modules to convert uart1, uart2 signals on my evaluation board. I am also using a PCA8575PW I2C IO expander to provide some digital outputs for my device. one of the outputs of the IO expander is used to drive the RS485 direction pins. So, using the RTS signal on UART to control the RS485 direction is out of question here.
I’ve successfully used i2c library in my C code to drive the direction pins and make the communication work, but I want to know if that is possible to somehow configure the uart(rs485) driver in linux to use the i2c expander pin instead of RTS to control the RS485 direction pin? I want to take the direction pin control mechanism out of user space, and do it in driver level
is it possible to define this functionality in the DTS file?
or
should I write a new driver for uart?
thank you in advance
Hello, Thank you for all your articles they are really helpful.
I need some help regarding our project. We have our customised board which is almost a replica of beaglebone black except we have used ‘AM3352’ processor instead of AM3358. We have loaded eeprom with BBB configuration and our board is able to boot. Problem is whenever the GUI starts kernel gets panic, throws stacktrace and gets freeze. Non GUI based image works smoothly on the same board.
As per specification of AM3352, it does not have inbuilt graphics accelerator. Other than this we do not have any additional extra interface on the board as compared to BBB.
So, what are the changes we need to make?
What changes we need to make in Device tree, uboot and kernel configuration? Please elaborate a bit.
Thanks in advance